Position Title: Analog Mixed-Signal CAD Intern
Location: Ho Chi Minh Viet Nam
Department: IC Design / CAD Engineering
Duration: [e.g., 4–6 months]
🎯 Role Overview
We are seeking a highly motivated CAD Intern to support our Analog Mixed-Signal (AMS) design team. This internship offers hands-on experience in developing and maintaining design automation tools, flows, and methodologies that enable efficient AMS IC development. You’ll work closely with experienced CAD and circuit designers to streamline design processes and ensure high-quality tapeouts.
🛠️ Key Responsibilities
- Assist in the development and maintenance of CAD tools and design flows for analog/mixed-signal IC design.
- Support layout automation, verification, and physical design rule checking (DRC/LVS).
- Help integrate and validate EDA tools (e.g., Cadence Virtuoso, Synopsys Custom Compiler).
- Automate repetitive design tasks using scripting languages (e.g., Python, Tcl, Skill).
- Collaborate with circuit and layout engineers to debug tool issues and improve productivity.
- Document CAD methodologies and provide training support to design teams.
📚 Qualifications
- Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Basic understanding of analog/mixed-signal IC design concepts.
- Familiarity with EDA tools such as Cadence Virtuoso, Synopsys, or Mentor Graphics.
- Experience with scripting languages (Skill, Python, Tcl, Shell).
- Strong analytical and problem-solving skills.
- Excellent communication and teamwork abilities.
🌱 What You’ll Gain
- Exposure to industry-standard AMS design flows and tools.
- Hands-on experience with IC design automation and verification.
- Mentorship from experienced CAD and design engineers.
- Opportunity to contribute to real silicon development projects.
✅ Preferred Skills (Nice to Have)
- Experience with version control systems (e.g., Git, Perforce).
- Knowledge of PDK integration and technology file management.
Familiarity with analog layout techniques and parasitic extraction.
Apply by sending email to: phu.vuong@asteralabs.com
