Job Description

Responsible for formal verification, RTL design, computer architecture, functional verification, and debugging.

Job Requirement

■ Final-year students or fresh graduates in Bachelor’s or Master’s programs in Computer Science, Electrical Engineering, or a related field.

■ The GPA >= 7.5 for fresh graduates is a plus.

■ Excellent analytical and problem-solving skills.

■ Basic skills n RTL and testbench coding.

■ Experience with C/C++, System Verilog, SVA, and UVM is a plus.

■ Good skills to read and write English documents and fluent English conversion are a plus.

■ Familiarity with any of the following will be an advantage:

• FPGA, ASIC, or SoC
• OOP program concept
• Formal verification
• Ethernet, PCIe, USB, or AMBA bus protocols