Position Title: RTL Design Intern
Location: Ho Chi Minh Viet Nam
Department: IC Design / CAD Engineering
Duration: [e.g., 4–6 months]
Role Overview
We are seeking a passionate and detail-oriented RTL Design Intern to join our digital design team. You will contribute to the development of high-performance digital IP and SoC subsystems, including datapath, control logic, and interface modules. This internship provides hands-on experience in SystemVerilog RTL design, synthesis, and simulation flows, working with experienced design and verification engineers on real silicon projects.
Key Responsibilities
- Implement digital modules such as finite state machines (FSMs), datapaths, FIFOs, serializers/deserializers, and bus interfaces (AXI, APB, etc.).
- Collaborate with the architecture and verification teams to define module specifications, test plans, and design reviews.
- Perform functional simulations, waveform debugging, and testbench integration using simulators such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
- Assist in synthesis and timing analysis (using tools like Design Compiler or Fusion Compiler), ensuring design meets area, power, and timing goals
- Document design intent, coding style, and verification results following team guidelines.
Qualifications
- Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Solid understanding of digital logic design (combinational and sequential circuits, pipelining, state machines).
- Knowledge of simulation and debugging tools (e.g., VCS, ModelSim, Xcelium).
- Understanding of clock/reset domains, timing closure, and synchronous/asynchronous design.
- Familiarity with synthesis concepts and design constraints (SDC, timing paths, clocking).
What You’ll Gain
- Learn the end-to-end digital design flow, from microarchitecture to gate-level synthesis.
- Gain exposure to EDA tools (Synopsys, Cadence, Mentor) used in top-tier semiconductor companies.
- Understand practical design considerations for timing, area, and power optimization.
- Opportunity to contribute to real IP or SoC tape-out projects.
Preferred Skills (Nice to Have)
- Experience with version control systems (e.g., Git, Perforce).
- Familiar with Verilog, SystemVerilog languages and has basic digital design knowledge.
Familiarity with some simulators : Questa, VCS, Xrun
Apply by sending your CV to: phu.vuong@asteralabs.com
